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On the intrinsic rent parameter and spectra-based partitioning methodologies.

, , , и . EURO-DAC, стр. 202-208. IEEE Computer Society Press, (1992)

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Harshawardhan Ramachandran

Muthupandi Ramachandran

Sheetal Ramachandran

Vimal Ramachandran

Haribaskar Ramachandran

 

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Combined topological and functionality based delay estimation using a layout-driven approach for high level applications., и . EURO-DAC, стр. 72-78. IEEE Computer Society Press, (1992)An Empirical Study on the Effects of Physical Design in High-Level Synthesis., , , и . VLSI Design, стр. 11-16. IEEE Computer Society, (1994)Incorporating the Controller Effects During Register Transfer Level Synthesis., и . EDAC-ETC-EUROASIC, стр. 308-313. IEEE Computer Society, (1994)On the intrinsic Rent parameter and spectra-based partitioning methodologies., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (1): 27-37 (1994)A performance driven logic synthesis system using delay estimator., , , , и . Great Lakes Symposium on VLSI, стр. 88-92. IEEE, (1994)Accurate layout area and delay modeling for system level design., , , , и . ICCAD, стр. 355-361. IEEE Computer Society / ACM, (1992)On the intrinsic rent parameter and spectra-based partitioning methodologies., , , и . EURO-DAC, стр. 202-208. IEEE Computer Society Press, (1992)Evaluating layout area tradeoffs for high level applications., и . IEEE Trans. Very Large Scale Integr. Syst., 1 (1): 46-55 (1993)LAST: a Layout Area and Shape function esTimator for high level applications., и . EURO-DAC, стр. 351-355. EEE Computer Society, (1991)Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (12): 1450-1460 (1994)