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Soft error rate estimation of combinational circuits based on vulnerability analysis.

, , and . IET Comput. Digit. Tech., 9 (6): 311-320 (2015)

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An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor., , , , and . VLSI-SoC, page 151-156. IEEE, (2007)FitAct: Error Resilient Deep Neural Networks via Fine-Grained Post-Trainable Activation Functions., , , and . DATE, page 1239-1244. IEEE, (2022)MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework., , , and . FPL, page 369-373. IEEE, (2021)CNT-count Failure Characteristics of Carbon Nanotube FETs under Process Variations., , , and . DFT, page 86-92. IEEE Computer Society, (2011)Statistical static performance analysis of asynchronous circuits considering process variation., , and . ISQED, page 291-296. IEEE Computer Society, (2009)Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations., , , , and . PATMOS, volume 6448 of Lecture Notes in Computer Science, page 126-136. Springer, (2010)Diagnosis of faults in template-based asynchronous circuits., , , and . SoC, page 38-41. IEEE, (2009)Leakage Power Reduction of Asynchronous Pipelines., , and . Journal of Circuits, Systems, and Computers, 20 (2): 207-222 (2011)Quantizing YOLOv7: A Comprehensive Study., , and . CoRR, (2024)Timing yield estimation of carbon nanotube-based digital circuits in the presence of nanotube density variation and metallic-nanotubes., , and . ISQED, page 703-710. IEEE, (2011)