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Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling., , , , , and . VLSID, page 201-206. IEEE, (2020)DiAG: a dataflow-inspired architecture for general-purpose processors., and . ASPLOS, page 93-106. ACM, (2021)BabelFish: Fusing Address Translations for Containers., , , , and . ISCA, page 501-514. IEEE, (2020)MESA: Microarchitecture Extensions for Spatial Architecture Generation., , , , , , , , , and . ISCA, page 49:1-49:14. ACM, (2023)Scratchpad memory optimizations for digital signal processing applications., , and . DATE, page 974-979. IEEE, (2011)Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices., , , , , , , , , and 2 other author(s). HPCA, page 61-72. IEEE Computer Society, (2017)ScalCore: Designing a core for voltage scalability., , , , , and . HPCA, page 681-693. IEEE Computer Society, (2016)Accordion: Toward soft Near-Threshold Voltage Computing., , and . HPCA, page 72-83. IEEE Computer Society, (2014)Workload and power budget partitioning for single-chip heterogeneous processors., , , , and . PACT, page 401-410. ACM, (2012)Fair share: Allocation of GPU resources for both performance and fairness., , and . ICCD, page 440-447. IEEE Computer Society, (2014)