Author of the publication

Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults.

, , , and . ICECS, page 357-360. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults., , , and . ICECS, page 357-360. IEEE, (2018)The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis., , , , and . ISCAS, page 1610-1614. IEEE, (2022)Fault masking ratio analysis of majority voters topologies., , and . LATS, page 1-6. IEEE, (2018)Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation., , and . VLSI-SoC, page 234-235. IEEE, (2019)Fault Tolerance Evaluation of Different Majority Voter Designs., , , , , and . ISCAS, page 185-189. IEEE, (2022)An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults., , , and . VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 69-88. Springer, (2019)Reliability evaluation of circuits designed in multi- and single-stage versions., , , , , , and . LASCAS, page 1-4. IEEE, (2018)Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems., , , , , , , , , and 2 other author(s). J. Electron. Test., 39 (4): 409-420 (August 2023)Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing., , , , and . SBCCI, page 1-6. IEEE, (2022)The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits., , , , and . ICECS, page 433-436. IEEE, (2018)