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Optical Interconnects Using Hybrid Integration of CMOS and Silicon-Photonic ICs.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1632-1637 (March 2024)

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Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper)., , , and . MWSCAS, page 1151-1154. IEEE, (2019)Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS., , , and . CICC, page 1-4. IEEE, (2011)A 0.18-μm CMOS fully integrated 0.7-6 GHz PLL-based complex dielectric spectroscopy system., , , , and . CICC, page 1-4. IEEE, (2014)A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (3): 672-684 (2019)A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects., , and . IEEE J. Solid State Circuits, 43 (5): 1235-1246 (2008)Analog Solutions of Discrete Markov Chains via Memristor Crossbars., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (12): 4910-4923 (2021)3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS., , , , , and . ISSCC, page 1-3. IEEE, (2015)Optical I/O technology for tera-scale computing., , , , , , , and . ISSCC, page 468-469. IEEE, (2009)A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET., , , , , , , , , and 6 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)56 Gb/s PAM-4 optical receiver frontend in an advanced FinFET process., , , , , , , , , and 1 other author(s). MWSCAS, page 1-4. IEEE, (2015)