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pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang, S. Shin, H. Park, S. Park, Y. Choi, H. Lee, K. Jeon, J. Lee, H. Ahn, K. Kim, J. Kim, S. Chang, H. Hwang, D. Kim, Y. Yoon, S. Hyun, J. Park, Y. Song, Y. Park, H. Kwon, S. Bae, T. Oh, I. Song, Y. Bae, J. Choi, K. Park, S. Jang, and G. Jin. ISSCC, page 390-391. IEEE, (2017)

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Ky ng Kim

Die Artikelstruktur in passiven zweisprachigen Wörterbüchern Deutsch-Koreanisch: Konzeption zur Erstellung eines zweisprachigen Lernerwörterbuchs Deutsch-KoreanischK. Kim. Uni Heidelberg, (2008)

Youngsang Kim

Ryong Kim

Bongcheol Kim

Kim Gerber

Other publications of authors with the same name

Organizational Virtual Communities: Exploring Motivations Behind Online Panel Participation.T. Daugherty, W. Lee, H. Gangadharbatla, K. Kim, and S. Outhavong. J. Comput. Mediat. Commun., (2005)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.T. Oh, H. Chung, Y. Cho, J. Ryu, K. Lee, C. Lee, J. Lee, H. Kim, M. Jang, G. Han and 16 other author(s). ISSCC, page 430-431. IEEE, (2014)A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.D. Kim, B. Song, H. Ahn, W. Ko, S. Do, S. Cho, K. Kim, S. Oh, H. Joo, G. Park and 37 other author(s). ISSCC, page 448-450. IEEE, (2022)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.J. Heo, K. Kim, D. Lee, C. Lee, D. Moon, K. Kim, J. Baek, S. Yoon, H. Yang, K. Kim and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications.H. Ahn, Y. Sung, Y. Kim, J. Kim, K. Kim, D. Lee, Y. Go, J. Lee, J. Jung, Y. Kim and 10 other author(s). A-SSCC, page 1-4. IEEE, (2023)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.H. Chi, C. Lee, J. Park, J. Heo, J. Jung, D. Lee, D. Kim, D. Park, K. Kim, S. Kim and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.C. Lee, H. Chi, J. Heo, J. Park, J. Jang, D. Lee, J. Jung, D. Lee, D. Kim, K. Kim and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)Distributing Periodic Workload Uniformly Across Time to Achieve Better Service Quality.J. Koh, K. Kim, and H. Shin. IPPS/SPDP Workshops, volume 1586 of Lecture Notes in Computer Science, page 413-417. Springer, (1999)

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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Ky ng Kim

Youngsang Kim

Ryong Kim

Bongcheol Kim

Kim Gerber

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kim, Kihan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Ky ng Kim

Youngsang Kim

Ryong Kim

Bongcheol Kim

Kim Gerber

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.