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Disambiguation of "Jin, Xuefan"

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A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface.

, , , , and . ESSCIRC, page 454-457. IEEE, (2012)

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Hong Jin

Hua Jing

Li Jin

Xiufang Jin

Depu Jin

 

Other publications of authors with the same name

A 21-Gb/s Dual-Channel Voltage-Mode Transmitter With Stacked NRZ and PAM4 Drivers., , , , and . IEEE Access, (2018)A 17.5-Gb/s transceiver with a MaxEye-based autonomous adaptation., , , , , , and . ISCAS, page 1-4. IEEE, (2017)A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth., , , , , and . IEEE J. Solid State Circuits, 55 (10): 2724-2733 (2020)A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface., , , , and . ESSCIRC, page 454-457. IEEE, (2012)A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (3): 522-530 (2018)A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth., , , , and . A-SSCC, page 83-86. IEEE, (2019)A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer., , , , , , , and . IEEE J. Solid State Circuits, 57 (10): 3083-3093 (2022)A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector., , , , , and . IEEE J. Solid State Circuits, 53 (10): 2994-3003 (2018)A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy., , , and . A-SSCC, page 1-4. IEEE, (2015)A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer., , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)