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Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (9): 1532-1545 (2016)

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Wavelet method for high-speed clock tree simulation., , , and . ISCAS (1), page 177-180. IEEE, (2002)Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit., , , , , , and . ISCAS, page 249-252. IEEE, (2016)Direct Nonlinear Order Reduction with Variational Analysis., , , , and . DATE, page 1316-1321. IEEE Computer Society, (2004)Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis., , , , , and . ISCAS, page 1-4. IEEE, (2017)PulsePrint: Single-arm-ECG biometric human identification using deep learning., , and . UEMCON, page 452-456. IEEE, (2017)A Memristor Crossbar-Based Computation Scheme with High Precision., , , and . CoRR, (2016)A novel wavelet method for noise analysis of nonlinear circuits., , , , and . ASP-DAC, page 471-476. ACM Press, (2005)Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network., , , , , and . DATE, page 1463-1468. IEEE, (2019)A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement., , , , and . ASICON, page 1-4. IEEE, (2013)C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (6): 899-912 (2017)