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A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers., , , , , , and . ISSCC, page 62-64. IEEE, (2011)A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS., , , , , and . ISSCC, page 374-376. IEEE, (2011)Session 18 overview: Full duplex wireless front-ends., , and . ISSCC, page 312-313. IEEE, (2017)A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors., and . IEEE J. Solid State Circuits, 32 (5): 736-744 (1997)A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers., , , , and . IEEE J. Solid State Circuits, 54 (3): 646-658 (2019)An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power., , , , and . ESSCIRC, page 176-179. IEEE, (2015)A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios., , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (3): 229-233 (2008)New Associate Editor.. IEEE J. Solid State Circuits, 53 (5): 1243 (2018)A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a., , , , , and . IEEE J. Solid State Circuits, 42 (12): 2860-2869 (2007)A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS., , , , , , and . IEEE J. Solid State Circuits, 43 (12): 2693-2705 (2008)