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Disambiguation of "Meher, Pramod Kumar"

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A fast 8×8 integer Tchebichef transform and comparison with integer cosine transform for image compression.

, , , and . MWSCAS, page 1294-1297. IEEE, (2013)

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Pramod Kumar Pandey

Pramod Kumar Magu

Pramod Kumar Bhatotia

Pramod Chandrashekhariah

Pramod Shah

 

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Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic., , and . IEEE Trans. Computers, 62 (6): 1170-1178 (2013)Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition., and . ISCAS, page 2910-2913. IEEE, (2009)Efficient coefficient partitioning for decomposed DA-based inner-product computation., and . ISCAS, page 406-409. IEEE, (2011)VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT., and . APCCAS, page 458-461. IEEE, (2006)Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT., and . IEEE Trans. Circuits Syst. Video Techn., 23 (2): 353-363 (2013)Improved Comb Filter based Approach for Effective Prediction of Protein Coding Regions in DNA Sequences., , and . J. Signal and Information Processing, 2 (2): 88-99 (2011)Nonlinear channel equalization for wireless communication systems using Legendre neural networks., , and . Signal Process., 89 (11): 2251-2262 (2009)Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (10): 1701-1713 (2016)Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm., and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 1091-1098 (2015)High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation., , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (7): 606-610 (2007)