( en | de | ru )

 

Disambiguation of "Mochizuki, Seiji"

Author of the publication

copydeleteadd this publication to your clipboard
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems.

, , , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2878-2887 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Seiji Miyashiro

Seiji Osawa

 

Other publications of authors with the same name

71% Reducing the memory bandwidth requirement for a multi-standard video codec by lossless compression of video using a combination of 2D-DPCM and Variable Length Coding., , , , , , and . ICICDT, page 1-5. IEEE, (2016)A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems., , , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2878-2887 (2017)Intra texture prediction based on repetitive pixel replenishment., , , and . ICIP, page 2933-2936. IEEE, (2012)A 342mW mobile application processor with full-HD multi-standard video codec., , , , , , , , , and 4 other author(s). ISSCC, page 158-159. IEEE, (2009)CGTI-Net: Deep-Learning-Based Object Detection Network for High-Resolution Aerial Images., , , and . IoTaIS, page 169-174. IEEE, (2023)A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 44 (4): 1184-1191 (2009)4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control., , , , , , , , , and 2 other author(s). ISSCC, page 56-58. IEEE, (2021)4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems., , , , , , , , , and . ISSCC, page 78-79. IEEE, (2016)A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder., , , , , , and . ASICON, page 71-74. IEEE, (2011)Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture., , , , , , , , , and . ASP-DAC, page 528-534. IEEE, (2009)