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Disambiguation of "Narayanan, Aravind Tharayil"

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An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.

, , , , , , and . ASP-DAC, page 1-2. IEEE, (2016)

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Thomas Tharayil

Aravind Sekhar

Aravind Pasula

Aravind Bedekar

Aravind Sundaresan

 

Other publications of authors with the same name

A tail-current modulated VCO with adaptive-bias scheme., , , and . ASP-DAC, page 36-37. IEEE, (2015)A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique., , , , , and . ASP-DAC, page 5-6. IEEE, (2016)An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation., , , , , , and . ASP-DAC, page 13-14. IEEE, (2017)A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR., , , , , , , , , and 16 other author(s). ISSCC, page 344-346. IEEE, (2019)A Pulse-Tail-Feedback LC-VCO with 700Hz Flicker Noise Corner and -195dBc FoM., and . IEICE Trans. Electron., 102-C (7): 595-606 (2019)A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz., , , , and . ESSCIRC, page 343-346. IEEE, (2014)A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock., , , , , , and . IEICE Trans. Electron., 102-C (4): 276-286 (2019)Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping., , , , , , , , and . ISSCC, page 462-464. IEEE, (2019)A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI., , , , , and . A-SSCC, page 285-288. IEEE, (2014)A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology., , , , , , , , , and 8 other author(s). ESSCIRC, page 237-240. IEEE, (2022)