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SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 57 (4): 1039-1048 (2022)

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Screenshot identification using combing artifact from interlaced video., , , , and . MM&Sec, page 49-54. ACM, (2010)SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1567-1571 (2022)Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2737-2747 (2017)Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1059-1063 (2016)Enhancing perceptual quality of watermarked high-definition video through composite mask., , , , and . IPTA, page 161-165. IEEE, (2010)Video Watermarking on Overlay Layer., , , , and . IIH-MSP, page 85-88. IEEE Computer Society, (2011)SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 57 (4): 1039-1048 (2022)Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM., , and . IEEE Access, (2021)SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation., and . ISCAS, page 1-4. IEEE, (2018)Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (4): 609-620 (2018)