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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

T. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck, P. Raghavan, A. Mercha, Z. Tokei, D. Verkest, A. Thean, and P. Wambacq. ESSDERC, page 102-105. IEEE, (2014)

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Jürgen Bömmels

Nicolaus Bömmels

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Impact of process variability on BEOL TDDB lifetime model assessment.K. Croes, D. Kocaay, I. Ciofi, J. Bömmels, and Z. Tökei. IRPS, page 5. IEEE, (2015)Constant voltage electromigration for advanced BEOL copper interconnects.B. Tang, K. Croes, N. Jourdan, J. Bömmels, Z. Tökei, I. Wolf, E. Wilcox, and T. McMullen. IRPS, page 2. IEEE, (2015)As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability.B. Tang, K. Croes, Y. Barbarin, Y. Wang, R. Degraeve, Y. Li, M. Toledano-Luque, T. Kauerauf, J. Bömmels, Z. Tökei and 1 other author(s). Microelectron. Reliab., 54 (9-10): 1675-1679 (2014)3D SRAM Macro Design in 3D Nanofabric Process Technology.D. Abdi, S. Salahuddin, J. Bömmels, E. Giacomin, P. Weckx, J. Ryckaert, G. Hellings, and F. Catthoor. IEEE Trans. Circuits Syst. I Regul. Pap., 70 (7): 2858-2867 (July 2023)Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow.E. Giacomin, J. Bömmels, J. Ryckaert, F. Catthoor, and P. Gaillardon. VLSI-SOC, page 34-39. IEEE, (2020)Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line.L. Kljucar, M. Gonzalez, I. Wolf, K. Croes, J. Bömmels, and Z. Tökei. Microelectron. Reliab., (2016)Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects.L. Kljucar, M. Gonzalez, K. Croes, I. Wolf, J. Messemaeker, G. Murdoch, P. Nolmans, J. Vos, J. Bömmels, E. Beyne and 1 other author(s). Microelectron. Reliab., (2017)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.T. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck and 6 other author(s). ESSDERC, page 102-105. IEEE, (2014)Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation.H. Zahedmanesh, M. Gonzalez, I. Ciofi, K. Croes, J. Bömmels, and Z. Tökei. Microelectron. Reliab., (2016)3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs.E. Giacomin, J. Bömmels, J. Ryckaert, F. Catthoor, and P. Gaillardon. VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 279-300. Springer, (2020)

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Disambiguation of "Bömmels, Jürgen"

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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

Please choose a person to relate this publication to

Jürgen Bömmels

Nicolaus Bömmels

Jürgen Schmidt

Jürgen Braun

Jürgen Meyer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bömmels, Jürgen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

Please choose a person to relate this publication to

Jürgen Bömmels

Nicolaus Bömmels

Jürgen Schmidt

Jürgen Braun

Jürgen Meyer

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.