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IBM POWER6 microarchitecture., , , , , , , , and . IBM J. Res. Dev., 51 (6): 639-662 (2007)The POWER8TM processor: Designed for big data, analytics, and cloud environments., , , , , , , , , and 10 other author(s). ICICDT, page 1-4. IEEE, (2014)Design of the Power6 Microprocessor., , , , , , , , , and 7 other author(s). ISSCC, page 96-97. IEEE, (2007)Transactional memory support in the IBM POWER8 processor., , , , , , , , and . IBM J. Res. Dev., (2015)POWER4 system microarchitecture., , , , and . IBM J. Res. Dev., 46 (1): 5-26 (2002)IBM POWER8 processor core microarchitecture., , , , , , , , , and 10 other author(s). IBM J. Res. Dev., (2015)Robust architectural support for transactional memory in the power architecture., , , , , and . ISCA, page 225-236. ACM, (2013)IBM POWER9 processor core., , , , , , , and . IBM J. Res. Dev., 62 (4/5): 2:1-2:12 (2018)Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors., , , , , , and . IBM J. Res. Dev., 49 (1): 167-188 (2005)