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Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test.

, , and . ATS, page 237-241. IEEE Computer Society, (2017)

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High-Frequency, At-Speed Scan Testing., , , , , , and . IEEE Des. Test Comput., 20 (5): 17-25 (2003)Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test., , and . ATS, page 237-241. IEEE Computer Society, (2017)The ABCs of ITC., and . IEEE Des. Test Comput., 27 (5): 80 (2010)Achieving High Test Quality with Reduced Pin Count Testing., , , , and . Asian Test Symposium, page 312-317. IEEE Computer Society, (2005)Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality., , , , , and . DATE, page 56-61. IEEE Computer Society, (2005)Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study., , , , and . VTS, page 223-228. IEEE Computer Society, (2005)ITC and the Future of Test - We've Won., and . IEEE Des. Test, 33 (6): 96 (2016)The Demand and Practical Approach for 100x Test Compression., and . VLSI-SoC, page 245-250. IEEE, (2006)Scan Compression Implementation in Industrial Design - Case Study., and . Asian Test Symposium, page 83-84. IEEE Computer Society, (2009)Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality, , , , , and . CoRR, (2007)