( en | de | ru )

 

Disambiguation of "Agarwal, Amit"

Author of the publication

copydeleteadd this publication to your clipboard
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS.

, , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Amit Agarwal

Regina Amith-Borchart

Menachem Amitai

Samuel Amiteye

Menachem Amitai

 

Other publications of authors with the same name

Leakage Power Analysis and Reduction for Nanoscale Circuits., , , , and . IEEE Micro, 26 (2): 68-80 (2006)Process variation in embedded memories: failure analysis and variation aware architecture., , , and . IEEE J. Solid State Circuits, 40 (9): 1804-1814 (2005)An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1074-1085 (2019)A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 44 (1): 107-114 (2009)A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS., , , , , , , and . IEEE J. Solid State Circuits, 48 (1): 128-139 (2013)A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 56 (4): 1082-1092 (2021)53 Gbps Native GF(2 4) 2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 767-776 (2011)2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors., , , , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2807-2821 (2012)Layer Hall effect in a 2D topological axion antiferromagnet, , , , , , , , , and 26 other author(s). Nature, 595 (7868): 521--525 (Jul 21, 2021)Co- Location Resistant Virtual Machine Placement in Cloud Data Centers., and . ICPADS, page 61-68. IEEE, (2018)