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Disambiguation of "Hsu, Steven"

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A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS.

, , , , , , , and . IEEE J. Solid State Circuits, 48 (1): 128-139 (2013)

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Eric Hsu

Yüanfang Hsü

Oscar Hsu

Eugene Hsu

Jing Hsu

 

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A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 843-856 (2021)A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS., , , , , , , and . VLSI Technology and Circuits, page 138-139. IEEE, (2022)2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators., , , , , , , , and . VLSI Technology and Circuits, page 22-23. IEEE, (2022)34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms., , , , , , , , , and . ESSCIRC, page 90-93. IEEE, (2018)25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 392-394. IEEE, (2020)A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS., , , , and . ISSCC, page 256-600. IEEE, (2007)A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS., , , , , , , and . ISSCC, page 182-184. IEEE, (2012)Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies., , , , and . ISLPED, page 122-127. ACM, (2003)