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Resonant clocking using distributed parasitic capacitance., , , , and . IEEE J. Solid State Circuits, 39 (9): 1520-1528 (2004)Efficient techniques for gate leakage estimation., , , and . ISLPED, page 100-103. ACM, (2003)A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits., , , and . ICCAD, page 689-692. IEEE Computer Society / ACM, (2003)Design methodology for a 1.0 GHz microprocessor., , , , , , , , , and 5 other author(s). ICCD, page 17-23. IEEE Computer Society, (1998)Area-oriented synthesis for pass-transistor logic., , , and . ICCD, page 160-167. IEEE Computer Society, (1998)Techniques for multilayer channel routing., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (6): 698-712 (1988)Technology trends and implications on SoC design.. SoCC, page 386. IEEE, (2011)Chameleon: a new multi-layer channel router., , , , , , and . DAC, page 495-502. IEEE Computer Society Press, (1986)Analysis and Optimization of Enhanced MTCMOS Scheme., , and . VLSI Design, page 234-239. IEEE Computer Society, (2004)The Effect of Wire Length Minimization on Yield., , and . DFT, page 97-105. IEEE Computer Society, (1994)