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Disambiguation of "Richards, Brian C."

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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.

, , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 51 (4): 930-942 (2016)

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Brian C Dennert

Brian C Castle

Rolf-Walter Briant

Benoît Briand

Gisela Richards

 

Other publications of authors with the same name

HDBinaryCore: A 28nm 2048-bit Hyper-Dimensional biosignal classifier achieving 25 nJ/prediction for EMG hand-gesture recognition., , , , , and . ESSCIRC, page 229-232. IEEE, (2023)Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment., , , , , , and . IEEE International Workshop on Rapid System Prototyping, page 148-. IEEE Computer Society, (2003)Design of Wireless Portable Systems., , , , , , , , , and 3 other author(s). COMPCON, page 169-176. IEEE Computer Society, (1995)Implementation of BEE: a real-time large-scale hardware emulation engine., , , and . FPGA, page 91-99. ACM, (2003)A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET., , , , , , , , , and . A-SSCC, page 305-308. IEEE, (2017)ASIC Design and Verification in an FPGA Environment., , , , , and . CICC, page 737-740. IEEE, (2007)A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications., , , , , , and . CICC, page 499-502. IEEE, (2009)A prototype user interface for a mobile multimedia terminal., , , , , , , , and . CHI 95 Conference Companion, page 81-82. ACM, (1995)4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET., , , , , , , , , and 2 other author(s). ISSCC, page 58-60. IEEE, (2021)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET., , , , , , , , , and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)