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Disambiguation of "Chiu, Pi-Feng"

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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.

, , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 51 (4): 930-942 (2016)

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Yü Chih Chiu

Pi Huang

pi!1031782362!

Pi Ovaskainen

Chung-wai Chiu

 

Other publications of authors with the same name

Improving Noise Tolerance of Hardware Accelerated Artificial Neural Networks., , , , and . ICMLA, page 797-801. IEEE, (2018)Bottom-up Memory Design Techniques for Energy-Efficient and Resilient Computing. University of California, Berkeley, USA, (2018)A double-tail sense amplifier for low-voltage SRAM in 28nm technology., , and . A-SSCC, page 181-184. IEEE, (2016)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements., , , , , and . IEEE J. Solid State Circuits, 45 (10): 2142-2155 (2010)Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks., , , , , and . ICRC, page 25-33. IEEE, (2019)An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS., , , , and . VLSI Circuits, page 61-62. IEEE, (2018)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor., , , and . A-SSCC, page 121-124. IEEE, (2016)A Binarized Neural Network Accelerator with Differential Crosspoint Memristor Array for Energy-Efficient MAC Operations., , , , and . ISCAS, page 1-5. IEEE, (2019)A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability., , , , , , , , , and 12 other author(s). ISSCC, page 200-202. IEEE, (2011)