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Disambiguation of "Onishi, Takayuki"

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A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level.

, , , , and . ISCAS (2), page 261-264. IEEE, (2004)

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Takayuki Sugimoto

Takayuki Sugimoto

Takayuki Shindo

Takayuki Saito

 

Other publications of authors with the same name

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture., , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2019)A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K., , , and . COOL Chips, page 1-3. IEEE Computer Society, (2017)A 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K., , , and . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 491-499 (2018)Image Pre-Transformation for Recognition-Aware Image Compression., , , , and . ICIP, page 2686-2690. IEEE, (2019)An MMT Module for 4K/120fps Temporally Scalable Video., , , , and . ISCAS, page 1-5. IEEE, (2019)Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level., , , , , , , , , and 1 other author(s). DATE, page 20002-20007. IEEE Computer Society, (2003)A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control., , , , , and . GLOBECOM, page 1-6. IEEE, (2019)4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay., , , , , and . ICECS, page 410-413. IEEE, (2019)A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level., , , , and . ISCAS (2), page 261-264. IEEE, (2004)Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure., , , , , , , , , and 3 other author(s). Hot Chips Symposium, page 1-24. IEEE, (2015)