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14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration., , , , , , , , , and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC., , , , , , , , , and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management., , , , , , , , , and 4 other author(s). ISSCC, page 342-343. IEEE, (2023)SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs., , , , , , , , and . IEEE Des. Test, 40 (6): 64-75 (December 2023)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components., , , , , , , , , and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)An adaptive low-power receiver architecture for IEEE 802.15.4 standard., and . I2MTC, page 600-603. IEEE, (2014)