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14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.

M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu, K. Chiu, G. Guglielmo, P. Mantovani, L. Piccolboni, G. Tombesi, D. Trilla, J. Wellman, E. Yang, A. Amarnath, Y. Jing, B. Mishra, J. Park, V. Suresh, S. Adve, P. Bose, D. Brooks, L. Carloni, K. Shepard, and G. Wei. ISSCC, page 262-264. IEEE, (2024)

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Julie Joseph

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SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs.G. Tombesi, J. Zuckerman, P. Mantovani, D. Giri, M. dos Santos, T. Jia, D. Brooks, G. Wei, and L. Carloni. IEEE Des. Test, 40 (6): 64-75 (December 2023)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.M. dos Santos, T. Jia, M. Cochet, K. Swaminathan, J. Zuckerman, P. Mantovani, D. Giri, J. Zhang, E. Loscalzo, G. Tombesi and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)Agile SoC Development with Open ESP : Invited Paper.P. Mantovani, D. Giri, G. Guglielmo, L. Piccolboni, J. Zuckerman, E. Cota, M. Petracca, C. Pilato, and L. Carloni. ICCAD, page 96:1-96:9. IEEE, (2020)DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.F. Gao, T. Chang, A. Li, M. Orenes-Vera, D. Giri, P. Jackson, A. Ning, G. Tziantzioulis, J. Zuckerman, J. Tu and 7 other author(s). CICC, page 1-2. IEEE, (2023)Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP.J. Zuckerman, P. Mantovani, D. Giri, and L. Carloni. CoRR, (2022)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.T. Jia, P. Mantovani, M. dos Santos, D. Giri, J. Zuckerman, E. Loscalzo, M. Cochet, K. Swaminathan, G. Tombesi, J. Zhang and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)Agile SoC Development with Open ESP.P. Mantovani, D. Giri, G. Guglielmo, L. Piccolboni, J. Zuckerman, E. Cota, M. Petracca, C. Pilato, and L. Carloni. CoRR, (2020)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.T. Tambe, J. Zhang, C. Hooper, T. Jia, P. Whatmough, J. Zuckerman, M. dos Santos, E. Loscalzo, D. Giri, K. Shepard and 4 other author(s). ISSCC, page 342-343. IEEE, (2023)Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs.J. Zuckerman, D. Giri, J. Kwon, P. Mantovani, and L. Carloni. MICRO, page 350-365. ACM, (2021)

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Disambiguation of "Zuckerman, Joseph"

Please choose a person to relate this publication to

Julie Joseph

Joseph Landsberg

Joseph Kugbe

Joseph Dehler

Joseph Thomas

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zuckerman, Joseph"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.

Please choose a person to relate this publication to

Julie Joseph

Joseph Landsberg

Joseph Kugbe

Joseph Dehler

Joseph Thomas

Other publications of authors with the same name

Disambiguation