Author of the publication

A Hardware-Efficient Block Matching Algorithm and Its Hardware Design for Variable Block Size Motion Estimation in Ultra-High-Definition Video Encoding.

, , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (2): 15:1-15:21 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Performance-driven mapping for CPLD architectures., , , and . FPGA, page 39-47. ACM, (2001)Algorithm/Accelerator Co-Design and Co-Search for Edge AI., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3064-3070 (2022)Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices., , , and . SLIP@DAC, page 1:1-1:8. ACM, (2018)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , and . DAC, page 7:1-7:6. ACM, (2016)Throughput-oriented kernel porting onto FPGAs., , , , and . DAC, page 11:1-11:10. ACM, (2013)C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs., , and . DAC, page 205:1-205:6. ACM, (2014)Optimality study of resource binding with multi-Vdds., , , and . DAC, page 580-585. ACM, (2006)A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation., , , , , and . DATE, page 1789-1794. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Behavioral-level IP integration in high-level synthesis., , , and . FPT, page 172-175. IEEE, (2015)High-level synthesis with behavioral level multi-cycle path analysis., , , , and . FPL, page 1-8. IEEE, (2013)