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Disambiguation of "Chang, Kevin K."

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Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization.

, , , , , , , , , and . SIGMETRICS, page 323-336. ACM, (2016)

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Alexander Ali Kevin

Fu-Chang Chang

Kevin Niwek

Kevin Niwek

Kevin Thurley

 

Other publications of authors with the same name

Improving DRAM Performance by Parallelizing Refreshes with Accesses., , , , , , and . CoRR, (2017)LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency., , , , , and . CoRR, (2018)Understanding and Improving the Latency of DRAM-Based Memory Systems.. CoRR, (2017)What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study., , , , , , , , , and 2 other author(s). SIGMETRICS (Abstracts), page 110. ACM, (2018)Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins., , , , , , and . CoRR, (2018)Reducing DRAM Refresh Overheads with Refresh-Access Parallelism., , , , , , and . CoRR, (2018)Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation., , , , , , and . ICCD, page 25-32. IEEE Computer Society, (2016)Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM., , , , , and . HPCA, page 568-580. IEEE Computer Society, (2016)SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure., , , , , , , , and . CoRR, (2018)High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems., , , , and . CoRR, (2018)