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Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.

, , , , , and . HPCA, page 568-580. IEEE Computer Society, (2016)

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Understanding the effects of wrong-path memory references on processor performance., , , and . WMPI, page 56-64. ACM, (2004)Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems., , , , and . CoRR, (2018)Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips., , , , , , , and . CoRR, (2016)Improving Multi-Application Concurrency Support Within the GPU Memory System., , , , , , , and . CoRR, (2017)Zwift: A Programming Framework for High Performance Text Analytics on Compressed Data., , , , and . ICS, page 195-206. ACM, (2018)Evaluating Homomorphic Operations on a Real-World Processing-In-Memory System., , , , and . IISWC, page 211-215. IEEE, (2023)CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off., , , , , , , and . ISCA, page 666-679. IEEE, (2020)Page overlays: an enhanced virtual memory framework to enable fine-grained memory management., , , , , , , and . ISCA, page 79-91. ACM, (2015)PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture., , , and . ISCA, page 336-348. ACM, (2015)IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors., , , , , , , and . ISCA, page 985-998. IEEE, (2021)