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Disambiguation of "Gupta, Aarti"

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Completeness bounds and sequentialization for model checking of interacting firmware and hardware.

, , and . CODES+ISSS, page 202-211. IEEE, (2015)

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Aarti Singh

Renee Gupta

Jan Chandra Gupta

Ajay Kumar Gupta

Ashutosh Kumar Gupta

 

Other publications of authors with the same name

Parametric Circuit Representation Using Inductive Boolean Functions., and . CAV, volume 697 of Lecture Notes in Computer Science, page 15-28. Springer, (1993)Symmetry Reduction in SAT-Based Model Checking., , , and . CAV, volume 3576 of Lecture Notes in Computer Science, page 125-138. Springer, (2005)SAT-Based Verification Methods and Applications in Hardware Verification., , and . SFM, volume 3965 of Lecture Notes in Computer Science, page 108-143. Springer, (2006)Lemma Synthesis for Automating Induction over Algebraic Data Types., , and . CP, volume 11802 of Lecture Notes in Computer Science, page 600-617. Springer, (2019)Trace-Based Symbolic Analysis for Atomicity Violations., , , and . TACAS, volume 6015 of Lecture Notes in Computer Science, page 328-342. Springer, (2010)Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique., , and . CAV, volume 5643 of Lecture Notes in Computer Science, page 398-413. Springer, (2009)Concurrent Test Generation Using Concolic Multi-trace Analysis., , , and . APLAS, volume 7705 of Lecture Notes in Computer Science, page 239-255. Springer, (2012)Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (8): 1513-1517 (2008)Property Verification Through the Symbolic Enumeration of Control Path Programs, , , and . (2009)Draft (2009), under submission. Please request srirams@nec-labs.com for a copy..Psym: Efficient Symbolic Exploration of Distributed Systems., , and . Proc. ACM Program. Lang., 7 (PLDI): 660-685 (2023)