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Disambiguation of "Palermo, Samuel"

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A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques.

, , , , , , and . IEEE J. Solid State Circuits, 55 (2): 439-451 (2020)

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Denis Palermo

Francesco Palermo

Mario Palermo

Christophe Palermo

Samuel Kodjo

 

Other publications of authors with the same name

A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (3): 672-684 (2019)A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization., , , , , and . IEEE J. Solid State Circuits, 51 (3): 671-685 (2016)A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications., , , , and . IEEE J. Solid State Circuits, 49 (11): 2560-2574 (2014)A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage., , , , and . IEEE J. Solid State Circuits, 52 (3): 657-668 (2017)A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects., , and . IEEE J. Solid State Circuits, 43 (5): 1235-1246 (2008)A 0.18-μm CMOS fully integrated 0.7-6 GHz PLL-based complex dielectric spectroscopy system., , , , and . CICC, page 1-4. IEEE, (2014)Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper)., , , and . MWSCAS, page 1151-1154. IEEE, (2019)Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS., , , and . CICC, page 1-4. IEEE, (2011)3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS., , , , , and . ISSCC, page 1-3. IEEE, (2015)A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter., , and . Microelectron. J., 43 (10): 687-696 (2012)