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On-Chip Multimedia Real-Time OS and its MPEG-2 Applications.

, , , and . RTCSA, page 200-203. IEEE Computer Society, (1999)

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Advanced concurrent design environment for multimedia system LSIs., , , , and . Syst. Comput. Jpn., 33 (14): 72-80 (2002)A Memory-based Architecture for MPEG2 System Protocol LSIs., , , and . ED&TC, page 500-507. IEEE Computer Society, (1996)Scalable architecture for use in an over-HDTV real-time codec system for multiresolution video., , , and . VCIP, volume 5150 of Proceedings of SPIE, page 1752-1759. SPIE, (2003)Control of muscle contraction, , and . 2 (4): 351-384-- (1969)Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level., , , , , , , , , and 1 other author(s). DATE, page 20002-20007. IEEE Computer Society, (2003)On-Chip Multimedia Real-Time OS and its MPEG-2 Applications., , , and . RTCSA, page 200-203. IEEE Computer Society, (1999)The Roles of Logic Synthesis Systems.. IFIP Congress, page 529. North-Holland/IFIP, (1989)A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems., , , , , , , , , and . CICC, page 177-180. IEEE, (2003)A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level., , , , and . ISCAS (2), page 261-264. IEEE, (2004)A CAD Process Scheduling Technique., , and . ICCAD, page 354-357. IEEE Computer Society, (1990)