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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, K. Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, T. Schram, B. Briggs, C. Lorant, E. Rosseel, A. Hikavyy, R. Loo, J. Geypen, D. Batuk, G. Martinez, J. Soulie, K. Devriendt, B. Chan, S. Demuynck, G. Hiblot, G. der Plas, J. Ryckaert, G. Beyer, E. Litta, E. Beyne, and N. Horiguchi. VLSI Technology and Circuits, page 284-285. IEEE, (2022)

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Igor Radisic

D Böttger

D Zeppenfeld

D Zumkeller

D Bruß

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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. Keersgieter, M. Hosseini and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)Barrier-free intermolecular proton transfer in the Uracil-glycine complex induced by excess electron attachmentM. Gutowski, I. Dabkowska, J. Rak, S. Xu, J. Nilles, D. Radisic, and K. Bowen. Eur. Phys. J. D, (2002)Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.A. Vandooren, N. Parihar, J. Franco, R. Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, K. Vandersmissen, W. Li and 15 other author(s). VLSI Technology and Circuits, page 330-331. IEEE, (2022)Long-range electron binding to quadrupolar moleculesC. Desfrancois, Y. Bouteiller, J. Schermann, D. Radisic, S. Stokes, K. Bown, N. Hammer, and R. Compton. Phys. Rev. Lett., (2004)Integration of a Stacked Contact MOL for Monolithic CFET.V. Vega-Gonzalez, D. Radisic, B. Chan, S. Choudhury, S. Wang, A. Mingardi, Q. Le, H. Decoster, Y. Oniki, P. Puttarame and 13 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.H. Mertens, M. Hosseini, T. Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Y. Oniki and 30 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.R. Ritzenthaler, E. Capogreco, E. Dupuy, H. Arimura, J. Bastos, P. Favia, F. Sebaai, D. Radisic, V. Nguyen, G. Mannaert and 12 other author(s). VLSI Technology and Circuits, page 306-307. IEEE, (2022)

BibSonomy

Disambiguation of "Radisic, D."

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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Please choose a person to relate this publication to

Igor Radisic

D Böttger

D Zeppenfeld

D Zumkeller

D Bruß

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Radisic, D."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Please choose a person to relate this publication to

Igor Radisic

D Böttger

D Zeppenfeld

D Zumkeller

D Bruß

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.