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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, K. Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, T. Schram, B. Briggs, C. Lorant, E. Rosseel, A. Hikavyy, R. Loo, J. Geypen, D. Batuk, G. Martinez, J. Soulie, K. Devriendt, B. Chan, S. Demuynck, G. Hiblot, G. der Plas, J. Ryckaert, G. Beyer, E. Litta, E. Beyne, and N. Horiguchi. VLSI Technology and Circuits, page 284-285. IEEE, (2022)

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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. Keersgieter, M. Hosseini and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)Isolation of nanowires made on bulk wafers by ground plane doping.R. Ritzenthaler, H. Mertens, A. Keersgieter, J. Mitard, D. Mocuta, and N. Horiguchi. ESSDERC, page 300-303. IEEE, (2017)Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors.S. Tyaginov, A. Makarov, A. El-Sayed, A. Chasin, E. Bury, M. Jech, M. Vandemaele, A. Grill, A. Keersgieter, M. Vexler and 2 other author(s). IRPS, page 6. IEEE, (2022)FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below.G. Eneman, A. Keersgieter, A. Mocuta, N. Collaert, and A. Thean. ICICDT, page 1-4. IEEE, (2015)Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study.B. Kaczer, R. Degraeve, M. Rasras, A. Keersgieter, K. de Mieroop, and G. Groeseneken. Microelectron. Reliab., 42 (4-5): 555-564 (2002)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process.D. Jang, M. Bardon, D. Yakimets, K. Miyaguchi, A. Keersgieter, T. Chiarella, R. Ritzenthaler, M. Dehan, and A. Mercha. ESSDERC, page 159-162. IEEE, (2013)Origins and implications of increased channel hot carrier variability in nFinFETs.B. Kaczer, J. Franco, M. Cho, T. Grasser, P. Roussel, S. Tyaginov, M. Bina, Y. Wimmer, L. Procel, L. Trojman and 11 other author(s). IRPS, page 3. IEEE, (2015)Towards high performance sub-10nm finW bulk FinFET technology.T. Chiarella, S. Kubicek, E. Rosseel, R. Ritzenthaler, A. Hikavyy, P. Eyben, A. Keersgieter, L. Ragnarsson, M. Kim, S. Chew and 10 other author(s). ESSDERC, page 131-134. IEEE, (2016)Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?T. Chiarella, L. Witters, A. Mercha, C. Kerner, R. Dittrich, M. Rakowski, C. Ortolland, L. Ragnarsson, B. Parvais, A. Keersgieter and 9 other author(s). ESSCIRC, page 84-87. IEEE, (2009)Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling.A. Veloso, G. Eneman, A. Keersgieter, P. Favia, A. Hikavyy, R. Chen, A. Jourdain, and N. Horiguchi. ICICDT, page 51-54. IEEE, (2022)

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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Please choose a person to relate this publication to

De-an Qiu

An De Vos

An Mengi

An You

An Luo

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Disambiguation of "Keersgieter, An De"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Please choose a person to relate this publication to

De-an Qiu

An De Vos

An Mengi

An You

An Luo

Other publications of authors with the same name

Disambiguation

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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.