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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, K. Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, T. Schram, B. Briggs, C. Lorant, E. Rosseel, A. Hikavyy, R. Loo, J. Geypen, D. Batuk, G. Martinez, J. Soulie, K. Devriendt, B. Chan, S. Demuynck, G. Hiblot, G. der Plas, J. Ryckaert, G. Beyer, E. Litta, E. Beyne, and N. Horiguchi. VLSI Technology and Circuits, page 284-285. IEEE, (2022)

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João Veloso

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Scaling CMOS beyond Si FinFET: an analog/RF perspective.B. Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. van Liempc, A. Veloso, A. Vandooren and 4 other author(s). ESSDERC, page 158-161. IEEE, (2018)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.T. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck and 6 other author(s). ESSDERC, page 102-105. IEEE, (2014)Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling.A. Veloso, G. Eneman, A. Keersgieter, P. Favia, A. Hikavyy, R. Chen, A. Jourdain, and N. Horiguchi. ICICDT, page 51-54. IEEE, (2022)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.T. Bao, A. Veloso, S. Sakhare, P. Matagne, J. Ryckaert, M. Perumkunnil, D. Crotti, F. Yasin, A. Spessot, A. Furnémont and 2 other author(s). DAC, page 13. ACM, (2019)Beyond-Si materials and devices for more Moore and more than Moore applications.N. Collaert, A. Alian, H. Arimura, G. Boccardi, G. Eneman, J. Franco, T. Ivanov, D. Lin, J. Mitard, S. Ramesh and 16 other author(s). ICICDT, page 1-5. IEEE, (2016)Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors.E. Simoen, A. Oliveira, A. Veloso, A. Chasin, R. Ritzenthaler, H. Mertens, N. Horiguchi, and C. Claeys. ASICON, page 1-4. IEEE, (2019)NBTI reliability of Ni FUSI/HfSiON gates: Effect of silicide phase.A. Shickova, B. Kaczer, A. Veloso, M. Aoulaiche, M. Houssa, H. Maes, G. Groeseneken, and J. Kittl. Microelectron. Reliab., 47 (4-5): 505-507 (2007)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. Keersgieter, M. Hosseini and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO.K. Serbulova, S. Chen, G. Hellings, A. Veloso, A. Jourdain, D. Linten, J. Boeck, G. Groeseneken, J. Ryckaert, G. der Plas and 3 other author(s). VLSI Technology and Circuits, page 431-432. IEEE, (2022)Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs.W. Chen, S. Chen, A. Veloso, K. Serbulova, G. Hellings, and G. Groeseneken. VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Disambiguation of "Veloso, Anabela"

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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Please choose a person to relate this publication to

João Veloso

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BibSonomy

Disambiguation of "Veloso, Anabela"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Please choose a person to relate this publication to

João Veloso

Other publications of authors with the same name

Disambiguation

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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.