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Binary Access Memory: An optimized lookup table for successive approximation applications.

, , , , and . ISCAS, page 1620-1623. IEEE, (2011)

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Analysis of back-end flash in a 1.5b/stage pipelined ADC., , and . ISCAS, page 2247-2250. IEEE, (2013)Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits., , , and . ISCAS, page 428-431. IEEE, (2012)Correlated jitter sampling for jitter cancellation in pipelined TDC., , , and . ISCAS, page 810-813. IEEE, (2012)Parameter variation analysis for voltage controlled oscillators in phase-locked loops., , , and . ISCAS, page 716-719. IEEE, (2008)Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer., and . ISCAS, page 1212-1215. IEEE, (2008)Analysis of supply and ground noise sensitivity in ring and LC oscillators., , , and . ISCAS (6), page 5986-5989. IEEE, (2005)An extended radix-based digital calibration technique for multi-stage ADC., and . ISCAS (1), page 829-832. IEEE, (2003)A 71dB dynamic range third-order ΔΣ TDC using charge-pump., , , and . VLSIC, page 168-169. IEEE, (2012)A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier., , , , and . VLSIC, page 1-2. IEEE, (2014)Jitter in high-speed serial and parallel links., , , , and . ISCAS (4), page 425-428. IEEE, (2004)