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A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI.

, , , and . VLSI-SoC, page 95-98. IEEE, (2019)

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Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI., , , , and . CoRR, (2019)FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing., , , and . CoRR, (2020)A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing., , and . Hot Chips Symposium, page 1-24. IEEE, (2020)Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (2): 530-543 (2020)Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores., , , and . IEEE Trans. Computers, 70 (2): 212-227 (2021)Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores., , , , , and . ISCAS, page 1-5. IEEE, (2021)FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (4): 774-787 (2021)An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication., , , , , , and . IEEE Trans. Computers, 71 (8): 1794-1809 (2022)Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra., , , , and . CoRR, (2023)An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication., , , , , , and . CoRR, (2020)