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sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI.

S. Mach, F. Schuiki, F. Zaruba, and L. Benini. VLSI-SoC, page 95-98. IEEE, (2019)

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Anke Benini

Jochen Benini

Aldo Albert Benini

Luca Rizzini

Luca Tranchini

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Origami: A 803-GOp/s/W Convolutional Network Accelerator.L. Cavigelli, and L. Benini. IEEE Trans. Circuits Syst. Video Techn., 27 (11): 2461-2475 (2017)A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets.F. Schuiki, M. Schaffner, F. Gürkaynak, and L. Benini. CoRR, (2018)Efficient Image Dataset Classification Difficulty Estimation for Predicting Deep-Learning Accuracy.F. Scheidegger, R. Istrate, G. Mariani, L. Benini, C. Bekas, and A. Malossi. CoRR, (2018)CAS-CNN: A deep convolutional neural network for image compression artifact suppression.L. Cavigelli, P. Hager, and L. Benini. IJCNN, page 752-759. IEEE, (2017)Design and Analysis of NoCs for Low-Power 2D and 3D SoCs.C. Seiculescu, S. Murali, L. Benini, and G. Micheli. Low Power Networks-on-Chip, Springer, (2011)A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets.F. Schuiki, M. Schaffner, F. Gürkaynak, and L. Benini. IEEE Trans. Computers, 68 (4): 484-497 (2019)A Minimally Invasive Low-Power Platform for Real-Time Brain Computer Interaction Based on Canonical Correlation Analysis.M. Salvaro, S. Benatti, V. Kartsch, M. Guermandi, and L. Benini. IEEE Internet of Things Journal, 6 (1): 967-977 (2019)SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs.C. Ferri, A. Marongiu, B. Lipton, R. Bahar, T. Moreshet, L. Benini, and M. Herlihy. CODES+ISSS, page 39-48. ACM, (2011)Dynamic thermal clock skew compensation using tunable delay buffers.A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, and M. Poncino. ISLPED, page 162-167. ACM, (2006)Contents provider-assisted dynamic voltage scaling for low energy multimedia applications.E. Chung, G. Micheli, and L. Benini. ISLPED, page 42-47. ACM, (2002)

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Disambiguation of "Benini, Luca"

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A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI.

Please choose a person to relate this publication to

Anke Benini

Jochen Benini

Aldo Albert Benini

Luca Rizzini

Luca Tranchini

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Benini, Luca"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI.

Please choose a person to relate this publication to

Anke Benini

Jochen Benini

Aldo Albert Benini

Luca Rizzini

Luca Tranchini

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI.