( en | de | ru )

 

Disambiguation of "Tosson, Amr M. S."

Author of the publication

copydeleteadd this publication to your clipboard
Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems.

, , , and . ISVLSI, page 62-67. IEEE Computer Society, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

M S Perzanowski

M S Khan

M S Jenny

Rahul M S

Rifaat Tosson

 

Other publications of authors with the same name

1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays., , , and . ASICON, page 12-15. IEEE, (2017)Error Resilience and Recovery of Process Induced Stuck-at Faults in MLP Neural Networks using Emerging Technology., , and . NANOARCH, page 1-6. IEEE, (2021)RRAM Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For HfO2/Hf 1T1R RRAM Memory Cell., , and . ACM Great Lakes Symposium on VLSI, page 227-232. ACM, (2016)A Novel 2T2R CR-based TCAM Design for High-speed and Energy-efficient Applications., , , , and . ACM Great Lakes Symposium on VLSI, page 33-38. ACM, (2022)Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design., , and . VLSI-SoC, page 368-373. IEEE, (2013)Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic Systems., , , and . ACM Great Lakes Symposium on VLSI, page 53-58. ACM, (2017)Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems., , , and . ISVLSI, page 62-67. IEEE Computer Society, (2017)A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (11): 3125-3137 (2017)A Novel Programmable Variation-Tolerant RRAM-based Delay Element Circuit., , , and . NANOARCH, page 1-2. IEEE, (2021)8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design., , , and . ACM Great Lakes Symposium on VLSI, page 239-244. ACM, (2016)