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Disambiguation of "Upadhyaya, Parag"

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A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS.

, , , , , , , , , , and . A-SSCC, page 233-236. IEEE, (2016)

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Parag Goyal

Parag Narvekar

Nikos Paragios

Parag Mogre

Parag Kinge

 

Other publications of authors with the same name

A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (7): 1783-1797 (2017)A new gain controllable on-chip active balun for 5 GHz direct conversion receiver., , , and . ISCAS (5), page 5115-5118. IEEE, (2005)A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS., , , , , , , , , and 6 other author(s). VLSIC, page 104-105. IEEE, (2012)A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (12): 3486-3502 (2017)3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies., , , , , , , , , and 7 other author(s). ISSCC, page 204-205. IEEE, (2023)A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET., , , , , , , , , and 6 other author(s). ISSCC, page 108-110. IEEE, (2018)A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET., , , , , , , , , and 5 other author(s). VLSI Circuits, page 47-48. IEEE, (2018)A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (8): 1932-1944 (2015)