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Disambiguation of "Sohn, Kyomin"

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A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.

, , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)

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Janina Söhn

Gerhard Sohn

Renate Söhn

Johann Söhn

Ewald Söhn

 

Other publications of authors with the same name

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product., , , , , , , , , and 6 other author(s). ISCA, page 43-56. IEEE, (2021)22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 330-332. IEEE, (2020)An Architecture of Sparse Length Sum Accelerator in AxDIMM., , , and . AICAS, page 1-4. IEEE, (2022)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)., , , , , , , , , and 9 other author(s). A-SSCC, page 169-172. IEEE, (2016)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer., , , , , , , , , and 4 other author(s). IEEE Micro, 42 (3): 20-30 (2022)A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture., , and . IEEE J. Solid State Circuits, 40 (1): 254-260 (2005)An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s., , , , , , and . IEEE J. Solid State Circuits, 58 (11): 3242-3252 (November 2023)An FPGA-based RNN-T Inference Accelerator with PIM-HBM., , , , , , and . FPGA, page 146-152. ACM, (2022)An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology., , , , and . IEEE J. Solid State Circuits, 41 (4): 823-830 (2006)