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Disambiguation of "Salahuddin, Sayeef S."

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On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs.

, , , , , , , and . VLSI Technology and Circuits, page 421-422. IEEE, (2022)

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Sarah Salahuddin

M Salahuddin

Salahuddin Ghazi Khan Vardag

S Danischewski

S Hilt

 

Other publications of authors with the same name

Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes., , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (3): 208-212 (2010)Negative Capacitance Transistors., and . Proc. IEEE, 107 (1): 49-62 (2019)Scanning the Issue., , , , , , , , , and 9 other author(s). Proc. IEEE, 108 (4): 483-484 (2020)Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies., , , , , , , , , and . CoRR, (2022)Logically Synthesized, Hardware-Accelerated, Restricted Boltzmann Machines for Combinatorial Optimization and Integer Factorization., , and . CoRR, (2020)Reducing signal-bias from MAD estimated noise level for DCT speech enhancement., , and . Signal Process., 84 (1): 151-162 (2004)Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack., , , , , , , , , and 3 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)FerroX : A GPU-accelerated, 3D Phase-Field Simulation Framework for Modeling Ferroelectric Devices., , , , , and . CoRR, (2022)Ultrathin Ferroelectricity and Its Application in Advanced Logic and Memory Devices.. IRPS, page 1-4. IEEE, (2021)A Density Metric for Semiconductor Technology Point of View., , , , , , , , and . Proc. IEEE, 108 (4): 478-482 (2020)