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Disambiguation of "Dosaka, Katsumi"

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A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform.

, , , and . IEICE Trans. Electron., 90-C (10): 1927-1935 (2007)

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Katsumi Nomura

 

Other publications of authors with the same name

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor., , , , , , , , , and . IEICE Trans. Electron., 91-C (9): 1409-1418 (2008)On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform., , , and . IEICE Trans. Electron., 92-C (3): 356-363 (2009)An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design., , , , , , , and . IEICE Trans. Electron., 89-C (11): 1519-1525 (2006)A 40GOPS 250mW massively parallel processor based on matrix architecture., , , , , , , , , and 2 other author(s). ISSCC, page 1616-1625. IEEE, (2006)Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (8): 1312-1315 (2007)Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (1): 334-345 (2007)Design methodology of embedded DRAM with virtual-socket architecture., , , , , , , and . IEEE J. Solid State Circuits, 36 (1): 46-54 (2001)A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 40 (1): 204-212 (2005)A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM., , , and . CICC, page 451-454. IEEE, (2005)A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs., , , , , and . IEEE J. Solid State Circuits, 42 (11): 2611-2619 (2007)