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Disambiguation of "Jain, Ankesh"

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A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS.

, , , , , and . ISSCC, page 336-338. IEEE, (2019)

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Gora Jain

Himalaya Jain

Arpit Jain

Tushar Jain

Prabhat Jain

 

Other publications of authors with the same name

Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface., and . ISCAS, page 1252-1255. IEEE, (2013)Deriving concentrators from binary sorters using half cleaners., , and . ReConFig, page 1-6. IEEE, (2017)A 0.4-V Gm-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR., , , , , and . IEEE J. Solid State Circuits, 53 (11): 3256-3267 (2018)Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique., , and . IEEE J. Solid State Circuits, 47 (7): 1615-1625 (2012)An Integrated Readout for Current Sensing based on a Σ∆ Modulator with Switched Capacitor Feedback., , , and . ESSCIRC, page 321-324. IEEE, (2019)System Level Modeling and Optimization of Hybrid Vibration Energy Harvesters., , and . ISCAS, page 1-5. IEEE, (2020)Effective Filtering of Requantization Error in Dual Quantized CTDSM using FIR DAC., , and . ISCAS, page 1-5. IEEE, (2019)Interferer Induced Jitter Reduction in Bandpass CT ΣΔ Modulators for Receiver Applications., , , , and . ISCAS, page 1-4. IEEE, (2018)Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback., and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (2): 434-443 (2018)A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance., , , , , and . IEEE J. Solid State Circuits, 55 (2): 344-355 (2020)