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Disambiguation of "Motomura, Masato"

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Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket.

, , , , , , , , and . CoRR, (2024)

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Masato Ishizaki

Masato Ikuta

Daniele Masato

 

Other publications of authors with the same name

Wrapper-based bus implementation techniques for performance improvement and cost reduction., , and . IEEE J. Solid State Circuits, 39 (5): 804-817 (2004)Cache-processor coupling: a fast and wide on-chip data cache design., , , and . IEEE J. Solid State Circuits, 30 (4): 375-382 (April 1995)F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems., , , , , and . ISSCC, page 506-508. IEEE, (2017)Advanced Devices and Architectures., , and . Principles and Structures of FPGAs, Springer, (2018)Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet., , , , , , , , and . ISSCC, page 1-3. IEEE, (2022)New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic., and . J. Syst. Archit., 48 (8-10): 285-310 (2003)Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner., , , , , , and . HCS, page 1-21. IEEE, (2021)A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers., , , , , , and . IEICE Trans. Inf. Syst., 105-D (12): 2019-2031 (December 2022)A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations., , , , , , and . MCSoC, page 478-485. IEEE, (2023)Decision Forest Training Accelerator Based on Binary Feature Decomposition., , , , , , and . FCCM, page 215. IEEE, (2023)