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BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 53 (4): 983-994 (2018)

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BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 53 (4): 983-994 (2018)APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control., , , , , , and . IPDPS Workshops, page 414-420. IEEE, (2022)Exploring optimized accelerator design for binarized convolutional neural networks., , , , , and . IJCNN, page 2510-2516. IEEE, (2017)Multicoated Supermasks Enhance Hidden Networks., , , , , , , and . ICML, volume 162 of Proceedings of Machine Learning Research, page 17045-17055. PMLR, (2022)A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers., , , , , , and . IEICE Trans. Inf. Syst., 105-D (12): 2019-2031 (December 2022)Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet., , , , , , , , and . ISSCC, page 1-3. IEEE, (2022)Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner., , , , , , and . HCS, page 1-21. IEEE, (2021)STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions., , , , , , , , , and . IEEE J. Solid State Circuits, 56 (1): 165-178 (2021)Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision., , , , , , , , , and . IEEE Access, (2024)Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks., , , , , , , , , and . IEICE Trans. Inf. Syst., 102-D (12): 2341-2353 (2019)