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Disambiguation of "Ueyoshi, Kodai"

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BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 53 (4): 983-994 (2018)

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Keiichi Kodaira

 

Other publications of authors with the same name

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 53 (4): 983-994 (2018)Exploring optimized accelerator design for binarized convolutional neural networks., , , , , and . IJCNN, page 2510-2516. IEEE, (2017)QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 54 (1): 186-196 (2019)DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 58 (1): 203-215 (2023)FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting., , , , , and . ReConFig, page 1-6. IEEE, (2016)Logarithmic Compression for Memory Footprint Reduction in Neural Network Training., , , , , , , , and . CANDAR, page 291-297. IEEE Computer Society, (2017)Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks., , , , , , , , , and . IEICE Trans. Inf. Syst., 102-D (12): 2341-2353 (2019)A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 692-703 (2021)DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2022)Accelerating deep learning by binarized hardware., , , , , , , and . APSIPA, page 1045-1051. IEEE, (2017)