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Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (8): 1487-1495 (2012)Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling., , , , , , , , , and 15 other author(s). ICICDT, page 145-148. IEEE, (2018)Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling., , , , , , , , and . ISCAS, page 2249-2252. IEEE, (2011)Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications., , , , , , , , , and 6 other author(s). ICICDT, page 1-4. IEEE, (2012)Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET., , , , , , , and . Microelectron. Reliab., (2018)Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?, , , , , , , , , and 9 other author(s). ESSCIRC, page 84-87. IEEE, (2009)Beyond-Si materials and devices for more Moore and more than Moore applications., , , , , , , , , and 16 other author(s). ICICDT, page 1-5. IEEE, (2016)