Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)Comprehensive 300 mm process for Silicon spin qubits with modular integration., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections., , , , , , , , , and 15 other author(s). VLSI Technology and Circuits, page 330-331. IEEE, (2022)Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling., , , , , , , , , and 15 other author(s). ICICDT, page 145-148. IEEE, (2018)Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET., , , , , , , and . Microelectron. Reliab., (2018)Towards high performance sub-10nm finW bulk FinFET technology., , , , , , , , , and 10 other author(s). ESSDERC, page 131-134. IEEE, (2016)Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling., , , , , , , and . ICICDT, page 51-54. IEEE, (2022)Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning., , , , , , , , , and 30 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)