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Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.

, , , , , , , , , , , , и . ISSCC, стр. 280-281. IEEE, (2008)

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Jung-Woo Lee

Won-Woo Lee

Woo-Kyun Lee

See-Woo Lee

Woo Bung Lee

 

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