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A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.

, , , , , , , , , и . ISSCC, стр. 378-380. IEEE, (2018)

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Parag Goyal

Parag Narvekar

Nikos Paragios

Parag Mogre

Parag Kinge

 

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