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A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 1973-1986 (2015)

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Energy impact in the design space exploration of loop buffer schemes in embedded systems., , , , and . VLSI-SoC, page 216-221. IEEE, (2013)Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS., , , , , , and . SiPS, page 151-156. IEEE, (2009)Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors., , , , , and . DATE, page 1608-1613. IEEE, (2009)Sub-word Handling in Data-parallel Mapping., , , , and . ARCS Workshops, volume P-200 of LNI, page 409-420. GI, (2012)A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 1973-1986 (2015)Exploiting finite precision information to guide data-flow mapping., , , , and . DAC, page 248-253. ACM, (2010)Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors., , , , , and . J. Signal Process. Syst., 64 (1): 75-92 (2011)Novel energy-efficient scalable soft-output SSFE MIMO detector architectures., , , , , and . ICSAMOS, page 165-171. IEEE, (2009)